In a MOS (metal oxide semiconductor) device, one of the most important techniques for increasing the device density is the isolation technique. That is, the technique for minimizing the non-active region (field region) for isolating unit elements is very important. Such isolation techniques have progressed from p-n junction isolation techniques for bipolar devices to the LOCOS (local oxidation of silicon) isolation technique which was introduced by E. Kooi and J. A. Appels in 1970. With the LOCOS technique, the densities of MOS devices and bipolar devices have greatly improved.
Meanwhile, the trend in the progress of DRAMs is for technical developments for increasing the density of DRAMs. Particularly, an isolation technique by which the area of the non-active regions can be reduced is a key to the improvement of semiconductor density.
The LOCOS technique has been used with processes having a minimum line width of 1.0 .mu.m (such as a 1 M DRAM) without difficulty. However, with the development of minimum line widths of 0.8 .mu.m (such as with a 4 M DRAM), the limit of the LOCOS method came to be recognized. Efforts for overcoming this difficulty were steadily made until the present time. An example of an improvement to the LOCOS method is the use of trench formed by etching the silicon substrate, with an insulator filled in the trench. This trench isolation technique has not been put to significant practical use, however, due to the technical difficulty involved. Most efforts now are directed to further improvement of the LOCOS isolation technique, and this improved method may be put into mass production.
The trend of improving the LOCOS technique is oriented to minimize the encroachment (bird's beak) of the oxide into the active region during oxidation. As illustrated in FIG. 1, in the general LOCOS method, bird's beak 16, which is caused by side oxidation, is grown in an elongated manner during the field oxidation along pad oxide layer (SiO.sub.2) 14, which is the under-layer of nitride layer 12. Further, the impurity which is implanted during the field ion implantation diffuses into the active region (where elements are to be formed), thereby reducing the area of the active region.
In an attempt to overcome the above described problems, as illustrated in FIG. 2, efforts were made to inhibit the growth of the bird's beak, which is caused by the oxidation along pad oxide layer (SiO.sub.2) 24 (which is an under-layer of nitride layer 21). That is, polysilicon buffer layer 23 is inserted between SiO.sub.2 layer 24 and nitride layer 21, which is the oxidation mask. This is the so-called polysilicon buffered LOCOS method, which was proposed in 1988 (IEDM, p. 100).
In addition to the above methods, a "SILO" method has been proposed (sealed interface local oxidation, 1988, IEEE Transaction Electron Devices, p. 96), and as well as a "SWAMI" (side wall masked isolation) method. With such improved methods, however, there remain problems to be solved.
In the case of the polysilicon buffered LOCOS, field oxide bird's beak 26 is reduced to some degree, but, when gate line formation and metallization are carried out after the LOCOS method, the formation of a pattern having a certain resolution on a photo resist is difficult due to the fact that the upper portion (the portion which is projected from the silicon substrate) of the field oxide is very large. Further, the field oxide cannot be formed deeply from the surface of the substrate, and, therefore, the channel length of the parasite field transistor is shortened, with the result that the punch-through characteristics are lowered, and the isolation feature is affected.
Meanwhile, in the case of the SWAMI isolation method, the problem of the bird's beak does not occur, but there are many problems in carrying out the method itself. That is, difficulties are encountered in etching the silicon substrate in an inclined form, whether a wet etching or a dry etching is applied. In the case of wet etching, an aqueous alkaline solution such as KOH or NaOH is used. In this method, the etching is possible only at a certain angle depending on the crystallization of the substrate, and, therefore, there is no slope control ability. For example, in the case of a 100 wafer, the etching is made at an angle of 45.degree. in the direction of 110, while K.sup.+ and Na.sup.+ ions contaminate the silicon substrate. In the case of dry etching, there are problems in controlling uniformity of the slope and repeated uniform formation.
In addition, there also are serious problems in the conventional LOCOS method. That is, the width and length of the active region are reduced so as to be suitable for a high density device, but the thickness of the field oxide is not reduced, and a heat cycle which is the same as that of the conventional method has to be retained. Further, a high concentration ion implantation has to be carried out for stably maintaining the punch-through voltage on the short channel isolating space. Therefore, the high concentration dopant of the field region diffuses sidewardly into the active region as with other conventional techniques and, therefore, the real reduction of the width of the active region becomes the same as that of conventional techniques. In accordance with the increase of the density, however, the active width in the design is very much reduced based on the design rule. (For example, the width of the active region for a 64 M DRAM is 0.4 .mu.m). The sideward diffusion amount .DELTA.W of the active region channel stop dopant relative to the width of the active region has resulted in a considerable loss of the width of the active region compared with conventional techniques. For example, as illustrated in FIG. 3, in the case where the semiconductor device has a designed active width W of 0.4 .mu.m and a length L of the active region, even if the amount .DELTA.W is 0.1 .mu.m, the diffusion encroachment occurs at opposite sides and, therefore, the relation is formed 0.4-2.DELTA.W =0.2 .mu.m. In the conventional LOCOS process, however, if field oxide having a thickness of 5000 .ANG. is formed, the value of .DELTA.W is estimated to be 0.15 to 0.2 .mu.m. Therefore, if the active width is reduced, the flow of current through the source and drain is restricted. Consequently, the performance of the transistor is deteriorated due to the lowering of the current driving capability and the rise of the threshold voltage.
Therefore, as described above, the conventional LOCOS method has many problems to be solved.